The present invention relates, in general, to receivers and, in particular, to receivers that can accommodate receiver input signals that exceed the power supply voltages of the integrated circuits that are included in the receivers.
As the core voltages of receivers (i.e., the optimum voltage at which the receiver circuits run) are reduced, input signals that are greater than the core voltages must be accommodated. Typically, interface circuits are included in the receiver that permit receiving input signals that are greater than the core voltages.
A conventional receiver that is xe2x80x9chigh voltage tolerant,xe2x80x9d such as the one shown in FIG. 1, includes an NFET pass-gate at the input to protect the receiver input stage, which is typically a CMOS inverter, from voltage levels at the gate of the input inverter that are higher than the input stage supply voltage. The NFET pass-gate at the PAD input serves to protect against the voltage level at the gate of the input stage of the receiver from rising to higher than approximately a threshold voltage below the input stage supply voltage VDDIN.
Because the NFET pass-gate protects against the voltage level at the gate of the input stage of the receiver from rising to higher than approximately a threshold voltage below the input stage supply voltage, a device, commonly called a xe2x80x9ckeeperxe2x80x9d device is included. This keeper device, typically a PFET, is used to pull the input to a full input supply voltage level when there is a logical xe2x80x9c1xe2x80x9d at the PAD input. The PFET keeper device shuts PFET 12 off completely when a logical xe2x80x9c1xe2x80x9d on the input will turn on an input stage NFET, thereby providing a xe2x80x9c0xe2x80x9d to the gate of PFET 16 turning it on. If the input device PFET 12 is not completely off, there will be a current leakage path directly from the input reference voltage to ground. The PFET keeper device has a source that is tied to the input supply voltage, a drain that is tied to the input stage inverter gate, and a gate that is tied to and controlled by the output of the input stage inverter.
Although the combination of the input NFET pass-gate and the PFET keeper device solve the problems of high voltage protection and turn off the input PFET, the keeper device presents another problem. When the input is switching from a logical xe2x80x9c1xe2x80x9d to a logical xe2x80x9c0xe2x80x9d or from a logical xe2x80x9c0xe2x80x9d to a logical xe2x80x9c1xe2x80x9d, there is a voltage range within which the PFET keeper device is turned on completely or partially at the same time that the input source pull down device is also on. This creates an input transient current spike that must be overcome by the input source in order to switch the input of the receiver. This makes difficult the use of passive pull down devices, such as resistors, to pull the input of the receiver low when the receiver is not being driven by an active device. If a pull down resistor is used, the value of the pull down resistor must be low enough to supply the current required to switch the receiver input stage and shut the keeper device off. Using a small pull down resistor can, in turn, result in power dissipation problems.
NFET pass-gate 10 serves to protect the receiver input inverter gate of the receiver input stage composed of a PFET 12 and an NFET 14 from high voltages by dropping high input voltages at input node PAD to approximately a threshold voltage below the VDDIN input stage supply voltage. As indicated above, a threshold voltage drop is produced by a voltage drop occurring at an interface in a structure acting as a pass-gate.
Because the NFET pass-gate 10 protects against the voltage level at the gate of the input stage of the receiver from rising to higher than approximately a threshold voltage below the input stage supply voltage, a xe2x80x9ckeeperxe2x80x9d device, namely a PFET 16, is used to pull the input to a full VDDIN input stage supply voltage level when there is a logical xe2x80x9c1xe2x80x9d at the input node PAD, with the PFET keeper device 16 shutting off PFET 12 completely because the logical xe2x80x9c1xe2x80x9d on the input node PAD will turn on the input stage NFET 14. Keeper device 16 will ensure that PFET 12 is completely shut off when NFET 14 and an NFET 18 are turned on when there is a logical xe2x80x9c1xe2x80x9d at input node PAD. NFET 18 is a receiver enable device that disables the receiver when activated by an enable source EN.
PFET 20 sets the receiver to a known state when activated by the enable source EN when the receiver is disable by NFET 18. PFET 20 serves to guarantee a known logical output level xe2x80x9c0xe2x80x9d at output node Z of a receiver output stage connected to the output of the receiver input inverter stage when the receiver is disabled. The receiver output stage is an inverter composed of a PFET 22 and an NFET 24. The VDD output stage supply voltage is the native voltage of the integrated circuit with which the receiver output Z must be compatible.
As set forth above, the pass-gate 10 and the keeper device 16 protect the receiver input stage from high voltages and ensure that there is not a leakage path in the receiver when a logical xe2x80x9c1xe2x80x9d is applied to input node PAD. However, the keeper device 16 presents another problem that must be considered for practical applications. When the voltage at input node PAD is being switched from a logical xe2x80x9c1xe2x80x9d to a logical xe2x80x9c0xe2x80x9d or vice versa, there is a time when the keeper device 16, is fully on or partially on at the same time as the pull down device driving input node PAD. This results in a current proportional to the size of the keeper device 16 that must be overcome by the device driving the input node PAD. Also, external pull down resistors or devices are sometimes required in system applications. Pull down devices will act against or offset the current of the keeper device which, in turn, will hinder the ability of the pull down device to keep a logical xe2x80x9c0xe2x80x9d at input node PAD. To overcome the keeper device 16, pull down devices are oversized to function reliably, which results in power consumption both on and off the integrated circuit.
By way of example, a 5 volt drop at input node PAD (i.e., a switching from a logical xe2x80x9c0xe2x80x9d to a logical xe2x80x9c1xe2x80x9d) is reduced to 2.7 volts by NFET pass-gate 10 for a VDDIN of 3.3 volts. The 2.7 volts logical xe2x80x9c1xe2x80x9d at the drain of NFET pass-gate 10 is enough to turn NFET 14 on and the logical xe2x80x9c0xe2x80x9d at the junction of NFET 14 and PFET 12 turns PFET 16 on, so that the drain of NFET pass-gate 10 is drawn to the 3.3 volt VDDIN supply voltage as PFET 16 is turned on. The 3.3 volts at the drain of NFET pass-gate 10 turn PFET 12 off maintaining the logical xe2x80x9c0xe2x80x9d at the junction of NFET 14 and PFET 12.
The deficiencies of the prior art show that a need still exists for improvement.
It is an objective of the present invention to provide a new and improved high voltage tolerant receiver.
It is another objective of the present invention to provide new and improved high voltage tolerant receivers that are not subject to the shortcomings and limitations of prior art high voltage tolerant receivers that have been described above.
A high voltage tolerant receiver, constructed in accordance with the present invention, includes an input stage supply voltage source, an output stage supply voltage source, a receiver input, and a receiver output. Also included in this high voltage tolerant receiver are a receiver input stage and an NFET pass-gate having a source connected to the receiver input, a gate connected to the input stage supply voltage source, and a drain connected to the receiver input stage. A high voltage tolerant receiver, constructed in accordance with the present invention, also includes a semiconductor device having a source connected to the input stage supply voltage source, a drain connected to the receiver input stage, and a gate connected to the input stage supply voltage source. A high voltage tolerant receiver, constructed in accordance with the present invention, further includes a receiver output stage connected to the output stage supply voltage source and between the receiver input stage and the receiver output.
It should be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive of the invention.
The features and advantages of a high voltage tolerant receiver, constructed in accordance with the present invention, will be more clearly understood from the following description when read in conjunction with the accompanying drawings.